MT8KTF25664AZ-1G6K1 Micron (2GB) Memory Module DDR3L SDRAM Non-ECC UDIMM Deals

Product Name: Micron (2GB) Memory Module DDR3L SDRAM Non-ECC UDIMM

Manufacturer: Micron

Product Features :

• 1. 1GB (128 Meg x 64), 2GB (256 Meg x 64), or 4GB (512 Meg x 64) 4
• 2. 240-pin, unbuffered dual in-line memory module (UDIMM) 2
• 3. Adjustable data-output drive strength 13
• 4. Backward-compatible to VDD = VDDQ = 1.5V ?0.075V 7
• 5. DDR3L functionality and operations supported as defined in the component data sheet 1
• 6. Fast data transfer rates: PC3-14900, PC3-12800, or PC3-10600 3
• 7. Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) 12
• 8. Fly-by topology 17
• 9. Gold edge contacts 15
• 10. Halogen-free 16
• 11. Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals 10
• 12. Reset pin for improved system stability 9
• 13. Serial presence-detect (SPD) EEPROM 14
• 14. Single-rank 11
• 15. Terminated control, command, and address bus 18
• 16. VDD = VDDQ = 1.35V (1.238-1.45V) 5
• 17. VDD = VDDQ = 1.5V (1.425-1.575V) 6
• 18. VDDSPD = 3.0-3.6V 8

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

NOTE: Image for Illustration Purposes ONLY.

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